A pipelined processor, such as a microprocessor for a personal computer or a digital signal processor, may include a data address generator (DAG) for generating speculative memory addresses for data which is transferred between memory and registers in the processor. In generating a data address, the DAG may update data address values used to calculate the data addresses. The updated data address values travel down the pipeline until they reach a write back (WB) stage, at which point they may be committed to an architectural file.
The DAG may use previously updated data address values that are still in the pipeline to generate a new data address. Some architectures include forwarding paths in each stage between the DAG, in an address calculation (AC) stage and the WB stage and utilize detection and multiplexing structures to locate and access the required updated values in the pipeline 102. Some problems associated with this type of architecture stem from the complexity of the logic required to detect data dependencies and to forward the appropriate operands to the execution units and increased power consumption due to the additional logic.